1 Field of the Invention
The present invention relates generally to a computer system including a system memory comprised of a dynamic random access memory (DRAM) array. More particularly, the invention relates to a memory controller for controlling data transfers between computer components and dynamic random access memory. Still more particularly, the invention relates to a memory controller capable of supporting different speed DRAM devices within a memory array.
2. Background of the Invention
Personal computers typically include dynamic random access memory ("DRAM") chips, commonly referred to as system memory. DRAM memory operates asynchronously meaning read and write requests do not necessarily coincide with a clock signal. Further, DRAM memory must be refreshed periodically to maintain the data stored in the chip. Normally, system memory includes banks of DRAM devices. Each memory bank may include as many as eight or nine memory chips. The number of banks provided in a computer system varies, but a typical range is between one and eight banks.
According to normal convention, the DRAM banks comprise the working memory of the system processor. The DRAM array connects to the memory controller via a memory bus, comprised of memory address lines, memory data lines, and various control lines. Data generally is transferred between the DRAM array and other components in two steps. First, the accessing component generates signals on the address lines representing the row address of the desired memory location, which are latched into the DRAM when the row address strobe (RAS) signal is asserted. At the next, or at subsequent, clock cycles, the DRAM latches in the column address signals when the column address strobe (CAS) signal is asserted. After the memory address has been determined, the memory array latches in data or drives out data, depending upon the status of the read/write (R/W) control signal.
The speed of memory devices is based upon certain timing parameters. These parameters require a certain period of to perform a memory operation. Because of these timing parameters, memory constructed with DRAM circuits is not always capable of responding to memory accesses within the time period allotted by the processor. In this event, external circuitry must signal to the processor that supplementary processor cycles, or wait states, are necessary before the data is ready on the data bus, or before data on the data bus can be stored in memory. In addition to slowing the system processor, wait states typically require use of the CPU host bus, thereby limiting use of that bus by other system components.
Recently, memory device manufacturers have introduced synchronous DRAM ("DRAM") to alleviate the memory bottleneck that occurs using conventional DRAM devices. Synchronous DRAM devices require a clock signal as a control input signal. SDRAM devices, like DRAM chips, are commonly organized into memory banks in an array. Many computer systems available today permit as many as eight bank in the memory array. The SDRAM device derives its name from the fact that all of the input signals (or commands) are accepted by the DRAM device on the rising edge of the clock signal, and thus are "synchronized" with the clock signal. The clock signal also allows data pipelining within the memory array and permits data to be output in a continuous stream.
SDRAM devices currently are available in different speeds (which typically is measured in units of frequency, such as megahertz which indicate the number of cycles per second for the device). Today, SDRAM devices are available as 66 MHz or 100 MHz devices, although higher speeds are anticipated. The price of SDRAM devices generally are dependent on frequency, with higher speed devices costing more.
The transfer and timing of address, data and control signals between a processor and a DRAM device is controlled by a memory controller. Memory controllers control transactions between the system memory and other components in the computer system, including the central processing unit. In some computer systems, the memory controller couples to a peripheral component interconnect ("PCI") bus to permit masters on the PCI bus to run cycles to the system memory. In accordance with normal convention, memory control units provide a clock signal to each bank in the SDRAM memory array. Often, because of loading problems and other concerns, memory controllers provide two separate output clock signals to clock up to eight memory banks, which each clock signal connected to up to four memory banks.
As faster microprocessors become available and implemented in computer designs, memory devices must operate faster to minimize processor wait states and to maintain compatibility with the processors. Because of the cost of memory devices, consumers prefer to salvage memory devices from old computers and re-use these memory devices in new computer systems. However, the use of faster processors in the new computer systems typically preclude the use of older, slower memory. Thus, as computer manufacturers offer faster computer systems, computer owners are unable to re-use memory devices from older computers. In large computer systems, such as file servers, the expenditure on system memory represents a substantial investment.
It would be advantageous to develop a computer system that is capable of using older memory devices when upgrading to a new computer system. At least one option has been suggested to accomplish this goal. That option is to run the computer system at the speed of the slowest memory device. Although faster memory devices will operate at the slower speed, the overall computer performance is compromised because data communications with the memory array are performed at a speed less than that at which the faster memory devices can operate.
It would thus be desirable to provide a computer system that is capable of implementing memory devices with different operating speeds. It would also be desirable if the computer system could optimize the performance of each memory device by performing transactions at the fastest possible speed with each memory circuit. By performing transactions at the maximum speed of each memory device, overall computer performance would be increased.
Despite the apparent advantage of a computer system capable of operating with SDRAM devices of different speeds, to date no such system has been built.